The present invention generally relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device comprising a delay circuit configured to delay an input signal to generate a delayed signal.
JP-A 2000-285672 discloses a semiconductor memory device comprising a delay circuit adapted to delay a row address strobe signal for a delay time to generate a latch enable signal. The delay time is shortened or elongated by a change in voltage. The disclosed semiconductor memory device prevents generation of the shortened delay time. The elongated delay time still exists.